Design and Optimization of a Quaternary Signed-Digit Adder for VLSI Applications

Abstract

The time required for addition is constrained by the carry propagation from the least significant bit to the most significant bit in the context of conventional binary adders. This lower bound increases in proportion to the operand's width. The quaternary signed-digit (QSD) number system, a redundant representation of radix-4 using {-3,...,3}, is used to overcome this constraint. Because each digit can be represented in several ways, addition can be done in a consistent amount of steps regardless of the number of digits. A carry-free QSD adder for VLSI applications is designed and optimized in this study. A compact three-bit two's complement digit encoding and two-step implementation are used in the adder. From each pair of digits, an intermediate carry and sum are generated. This prevents subsequent digit additions from generating a carry. All digit slices are reduced to tiny two-level networks, and the adder is a parallel array of identical slices. Due to generating logic enhancement, it has been decreased to this level. The design is compared to ripple-carry, carry-lookahead, carry-select, and redundant-binary adders in power, transistor count, and latency using a transistor-level approximation in a 45 nm CMOS flow. The normal data shown here show that worst-case addition latency is consistent from 8 to 64 digits. In contrast to binary adders' growing delay, the transistor's cost is linearly related to a ripple-carry adder. The numerical values provided are for illustration only; the reader should duplicate them using SPICE data and synthesis.